1. Field of the Invention
The present invention relates to a method of implementing an injection molded soldering process for three-dimensional structures, particularly, such as directed to three-dimensional semiconductor chip stacking. Furthermore, the invention is also directed to an arrangement for implementing the injection molded soldering (IMS) process and to a product obtained thereby.
Basically, in the current state of the technology, in implementing the forming or manufacture of so called three-dimensional semiconductor chip stacking, there is employed an injection molded soldering (IMS) process, which may also be referred to as a “C4NP” process (Controlled Collapse Chip Connection New Process). In essence, the IMS process may be considered a transfer mold process in which a mold, which is equipped with a plurality of sites for the placement of solder, such as cavities formed in a mold plate into which the solder can be positioned or injected, and wherein these sites may be provided at various locations and possess diverse geometries. Once the mold is filled with the unique and required configurations of solder in the placement locations, the formed material or solder can then be transferred to a semiconductor die or module and serve as a suitable interconnect for the semiconductor chip or chips.
The present state of the technology in manufacturing stacked semiconductor chips in various aspects normally employs the use of wire bonds which lead from a substrate to the respective semiconductor chip, and upon occasion as required, from semiconductor chip to semiconductor chip in the diverse superimposed or stacked layers of the structure. In some instances, a die can be thinned and through vias formed for direct semiconductor chip-to-chip joining, whereupon a dielectric material may then thereafter suitably encapsulate the structure, as is well known in the art.
Other more recent advances in the technology employ solder, such as solder balls and/or solder bumps for implementing various methods in effecting the stacking of semiconductor chips. In that instance, individual units or modules may have the chips mounted on dielectric layers, and provided with conductive traces on the dielectric layers interconnecting contacts on the semiconductor chips with terminals, which are disposed in peripheral regions of the dielectric layers.
Still further advances in the technology combine the above-mentioned concept of wire bonding the superimposed semiconductor chip layers and solder interconnections, wherein the solder connections may, upon occasion, pass through vias, which are formed in materials connecting the semiconductor chip layers, and wherein various pads are then connected to the interconnecting traces by means of wire bonds and then suitably encapsulated in a dielectric material.
However, the extent of the presently continuous advances in the technology in the formation or evolution of ever denser or miniaturized three-dimensional electronic packaging arrangements and other improvements imparted to such electronic packaging; for example, in the employment of superimposed layers of semiconductor chips or electronic components, are subject to limitations or restrictions in their abilities to provide a comprehensive structure, which is capable of effectively combining various sizes and configurations of solder interconnects on a single level, while at the same time be able to accommodate other electronic packages and components which are present within the stack of semiconductor chips or the three-dimensional package which has been formed.
2. Discussion of the Prior Art
Various prior art publications are presently in existence, which either provides for wire bonding or combinations of solder connections and wire bonding, such as for multiple layers of semiconductor chips or similar components of electronic package arrangements.
In connection with the foregoing, wire-bonding methods for multiple electronic layers, such as semiconductor chips, are illustrated in Pflughaupt, et al., U.S. Pat. No. 6,913,949 B2, wherein a stacked chip assembly includes individual units having chips mounted on dielectric layers and traces on the layers interconnecting contacts of the chips with terminals, which are located in the peripheral regions of the dielectric layers. In that manner, there are provided solder connections and solder bumps for chip stacking.
Pursuant to the prior art, a combination of wire bonding and solder interconnections for multiple layers of semiconductor chips is disclosed in Akram, et al., U.S. Pat. No. 6,222,265 B1, wherein a semiconductor chip package includes multiple stacked substrates having flip chips attached to a substrate with chip-on-dashboard assembly techniques utilizing combinations of electrical connections through the use of solder, and also in a combination with wire bond connections.
The foregoing patent publications provide disclosures which are limited in their particular abilities to meet the requirements of the ever-increasingly demanding electronic packaging technologies, and whereby the current limitations in structure and configuration are inventively solved by the present invention, which provides various structures that are rendered available through the unique IMS processes, so as to produce an improved and simplified three-dimensional semiconductor chip stacking structure.